1. Field of Invention
The present invention relates to an access control device that executes access control when a plurality of masters access a shared memory, and more particularly relates to a technique for improving responsiveness to an access request from a master whose occurrence of the access request is difficult to predict.
2. Description of the Related Art
There has been a system in which two types of masters share a same memory. One type of the masters requires access to be guaranteed at a predetermined rate within a fixed period. The other type of the masters (hereinafter referred to as processor) requests access to the memory irregularly and thus is difficult to predict the frequency of the access requests. Such a system has an arbitration circuit that arbitrates between the master and the processor to prevent an access conflict over the memory therebetween. Such arbitration circuits often execute access control by setting access priorities for the master and the processor. The following Patent Documents 1 and 2 disclose techniques to improve responsiveness to an access request from the processor in the above-described system.
For example, Patent Document 1 discloses a technique that permits the master to only access the memory with a predetermined frequency and normally prioritizes access of the processor. In the technique disclosed by patent Document 2, normally, an access priority of the processor is set to be low, and an access priority of the master is set to be high. However, if an access request of the processor occurs, and access to the shared memory is granted, the priority of the next access request from the processor is set to be higher than the other master.
[Patent Document 1] Japanese Laid-open Patent Application No. 2000-207355; and
[Patent Document 2] Japanese Laid-open Patent Application No. 2002-304368.